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摘要: 為了降低硬件開銷，越來越多的加法器電路采用傳輸管邏輯來減少晶體管數量，同時導致閾值損失、性能降低等問題。本文通過對擺幅恢復邏輯與全加器電路的研究，提出一種基于擺幅恢復傳輸管邏輯（Swing restored pass transistor logic, SRPL）的全加器設計方案。該方案首先分析電路的閾值損失機理，結合晶體管傳輸高、低電平的特性，提出一種擺幅恢復傳輸管邏輯的設計方法；然后，采用對稱結構設計無延時偏差輸出的異或/同或電路，利用MOS管補償閾值損失的方式，實現異或/同或電路的全擺幅輸出；最后，將異或/同或電路融合于全加器結構，結合4T XOR求和電路與改進的傳輸門進位電路實現擺幅恢復的高性能全加器。在TSMC 65 nm工藝下，本文采用HSPICE仿真驗證所設計的邏輯功能，與文獻相比延時降低10.8%，功耗延時積（Power-delay product, PDP）減少13.5%以上。Abstract: The adder circuit is the core component of the high-performance system-on-chip (SoC). It is also important in image and voice encryption. The full adder circuit is a basic unit with a very high reuse rate among all the units. Therefore, the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems. In recent years, numerous researchers have studied the design of advanced adder circuits, which are characterized by high speed and low power consumption. To reduce the hardware overhead, an increasing number of adder circuits utilize the transmission tube logic to reduce the number of transistors. However, this method also brings about several negative effects, such as threshold loss and performance degradation. In this paper, by studying the swing recovery logic and full adder circuit, we proposed a full adder design scheme based on swing restored pass-transistor logic (SRPL). First, the threshold loss mechanism of the circuit was analyzed, and the characteristics of the high-efficiency transmission of high-level and low-level transistors were considered; then the design method of the swing recovery transmission tube logic was developed. We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output. The two-shot MOS tube was used to compensate the threshold loss to realize the full swing output of the XOR/XNOR circuit. Finally, we fused the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum circuit and the improved transmission gate carry circuit to implement the high-performance full adder for swing recovery. In the TSMC 65 nm process, the logic function of our method was verified by HSPICE simulation. Compared with the conventional approach, the delay is reduced by 10.8%, and the power-delay product (PDP) is reduced by more than 13.5%. The design method of low delay and full swing output of the SRPL circuit can be further applied to the design of other logic circuits, further promoting the practical process of the SRPL circuit.
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Key words:
- XOR/XNOR circuit /
- swing recovery /
- high-performance full adder /
- threshold loss /
- full swing
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圖 1 3T XOR/XNOR電路和傳輸管傳輸狀態分析。（a）異或/同或電路；（b）NMOS高電平傳輸狀態；（c）PMOS低電平傳輸狀態
Figure 1. 3T XOR/XNOR circuit and the transition analysis by pass transistor: (a) XOR/XNOR circuit; (b) logic “1” transition by NMOS; (c) logic “0” transition by PMOS
圖 2 改進型異或/同或電路與RC模型。（a）改進型異或/同或電路；（b）AB=11 異或電路RC模型；（c）AB=00 同或電路RC模型
Figure 2. Improved XOR/XNOR circuit and RC model: (a) improved XOR/XNOR circuit; (b) RC model of XOR circuit for AB=11; (c) RC model of XNOR circuit for AB=00
圖 4 異或/同或電路輸出電平對比。（a） XOR；（b） XNOR
Figure 4. Comparison of XOR/XNOR circuit output levels: (a) XOR; (b) XNOR
圖 6 求和電路與進位電路。（a）基于傳輸門的4T XOR求和電路；（b）基于傳輸門的進位電路；（c）改進的傳輸門進位電路
Figure 6. Sum circuit and carry circuit: (a) 4T XOR sum circuit based on transmission gate; (b) carry circuit based on transmission gate; (c) improved carry circuit based on transmission gate
圖 9 擺幅恢復7T XOR/XNOR電路仿真結果。（a）仿真波形圖；（b）不同負載下PDP對比
Figure 9. Swing recovery of 7T XOR/XNOR circuit: (a) simulation waveform; (b) PDP results under different load conditions
圖 10 不同電壓與不同負載下全加器電路仿真結果。（a）不同電壓下全加器電路功耗對比；（b）不同電壓下全加器電路延時對比；（c）不同電壓下全加器電路PDP對比；（d）不同負載下全加器電路PDP對比
Figure 10. Simulation results of full adder circuit under different voltages and loads: (a) power results for different voltages; (b) delay results for different voltages; (c) PDP results for different voltages; (d) PDP results under different load conditions
表 1 擺幅恢復7T XOR/XNOR電路與相關文獻比較結果
Table 1. 7T XOR/XNOR circuit and comparison results of related literature
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中文字幕在线观看表 2 全加器電路與相關文獻比較結果
Table 2. Full adder circuit and related literature comparison results
Full Adder Numbers of Transistors Area/(17.78 μm2) Threshold loss Delay/ps Power/μW PDP/aJ Improvement PDP/% SERF[4] 10 0.80 YES 188.23 3.68 692.69 11.5 10T[5] 10 0.77 YES 173.62 3.24 562.53 28.1 CMOS[7] 28 1.66 NO 154.01 4.24 653.00 16.6 TGA[8] 20 1.64 NO 120.60 4.57 551.14 29.6 TFA[9] 16 1.23 NO 117.33 4.48 525.64 32.8 14T[21] 14 1.00 NO 194.75 4.02 782.90 0 DPL[22] 28 2.09 NO 125.81 4.61 580.00 25.9 CPL[24] 32 2.68 NO 112.52 5.85 658.24 16.0 Hybrid[25] 16 1.47 NO 116.35 4.65 541.03 30.9 Proposed 26 1.73 NO 100.40 4.53 454.81 41.9
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